Automated HDL modifying apparatus and computer-readable recording medium in which program for automatically modifying HDL is recorded

ABSTRACT

An apparatus is provided for automatically modifying serious semantic grammar errors in an HDL description and to clearly show the modified portions. For these purposes, the apparatus includes: means for detecting a portion in which variables on the right and the left sides of an assignment statement are inconsistent in type; a template for converting the type of the variable on the right side of the assignment statement into that of the variable on the left side; means for modifying the portion into a correct description by applying the type conversion function to the right side of the assignment statement having the portion; and means for attaching a comment about the modification to the modified portion, and is used to automatically modify inappropriate descriptions in the design information of an electronic system or of a logic circuit described in a hardware description language such as VHDL and Verilog-HDL.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an apparatus for automaticallymodifying inappropriate descriptions in the design information ofelectronic systems or of logic circuits, which is described in ahardware description language (HDL) such as VHDL {VHSIC (Very High SpeedIntegrated Circuit) HDL} and Verilog-HDL. And the invention relates alsoto a computer-readable recording medium in which a program forautomatically modifying such inappropriate descriptions is recorded.

[0003] 2. Description of the Related Art

[0004] At designing semiconductor integrated circuits such as LSI (LargeScale Integration), HDLs, such as VHDL and Verilog-HDL, are used todescribe the design information of their logic circuits. In contrast toordinary software programming languages, HDLs are suitable for use indescribing the functions and the structure of electronic systems andlogic circuits, and particularly in describing hierarchy designs,elevating the design level from a logic gate level to a microarchitecture level. On the basis of the design information (hereinafteralso called “HDL description”) described in an HDL, a logic circuit(netlist) is automatically synthesized by a logic synthesis tool.

[0005] Prior to the logic synthesis performed, or prior to inputting anHDL description to the logic synthesis tool, the HDL description ischecked (syntax check) for grammar errors. On the occasion of thegrammar error check, there could be employed such techniques asdisclosed in the following publicized applications.

[0006] For example, in Japanese Unexamined Patent ApplicationPublication No. HEI 2-294736, rather minor syntactic grammar errors,such as that a semicolon “;”, required at the end of each statement, isomitted, are detected to be automatically modified. With this techniqueemployed, even if a “;” is omitted at the end of a statement in a sourceprogram, the “;” can be automatically inserted.

[0007] Further, in Japanese Unexamined Patent Application PublicationNo. HEI 6-44081, if the types of variables disagree between on the rightside and the left side of an assignment statement in an input sourceprogram described in a PASCAL language, an error message is output fornotifying the occurrence of the disagreement.

[0008] If an HDL description is checked for grammar errors using thetechnique disclosed in Japanese Unexamined Patent ApplicationPublication No. HEI 2-294736, it is possible to automatically modify theabove syntactic grammar errors (minor ones), whereas it is impossible toautomatically modify semantic grammar errors (serious ones), such asthat the types of variables on the both sides of an assignment statementdisagree.

[0009] Accordingly, as to the semantic grammar errors, it has beennecessary for a designer (user) to modify them by manual operation,making reference to error messages output from an HDL processor system.At that time, since the error messages do not specify what modificationsare required, it is often impossible to resolve such a semantic grammarerror in one modification step, thereby becoming a burden on thedesigner. Additionally, since the semantic grammar errors occur in arelatively high frequency, their modifications have been putting aconsiderable burden on the designer.

[0010] Still further, after an automatic modification of the HDLdescription performed, it is still necessary for a designer to evaluatewhether the modification having been carried out complies with thedesigner's intention, or whether the modification thus carried out isthe appropriate one. In the conventional techniques, however, since theresult of the modification shows no sign nor mark indicating where theactual modification performed, difficulties are confronted inacknowledging where and in what way the modification has been performed,thereby imposing a significant burden on the designer.

[0011] If an HDL description is checked for grammar errors using thetechnique disclosed in Japanese Unexamined Patent ApplicationPublication No. HEI 6-44081, a designer is merely notified, with anerror message, of an occurrence of a semantic grammar error ofinconsistency in variable type between the both sides of an assignmentstatement, but the grammar error would never be automatically modified.Additionally, even if the designer is notified with the error messagewhere the error occurs and what the error is, the designer is not alwaysbe so familiar with all the grammar errors that the designer'stime-consuming manual modification, with reference to grammar textbooksor something, has often been necessitated, thus imposing an extremeburden on the designer.

[0012] In the meantime, with the conventional techniques, it is merelypossible to detect grammar errors, but meanwhile, it is impossible todetect or automatically modify the portions (inappropriate descriptions)which are not grammar errors but should be considered in view of circuitdesigning.

[0013] So far, a style checker has been suggested which detects theportions violating naming rules or logic synthesis description rules(rules defining logic synthesis-capable descriptions), and outputs thespecification of the violation. These portions do not correspond togrammar errors but should be considered in view of circuit designing.This style checker, however, is merely capable of outputting what theviolation is, and incapable of automatically modifying the HDLdescription so as to evade the violation. Accordingly, the designer hadto manually resolve the violation, making reference to the stylechecker's error message, thereby bearing a considerable burden. Inparticular, in case where two or more designers are involved in circuitdesigning in an HDL, there is a high possibility of multiple occurrencesof the naming rule violations, which would necessitate a great amount ofeffort in their modifications.

[0014] Further, in the conventional techniques, some of theinappropriate HDL descriptions, which are not grammar errors butviolates rules defining wire connections or the rules that should beconsidered in view of a hierarchical circuit design, cannot be detectedby the front-end (language processor) but by the back-end (logicsynthesis tool or verification tool). Even though such inappropriatedescriptions are due to the designer's careless mistakes, it isdifficult to find out them in an early stage, and is of coursethoroughly difficult to automatically modify the descriptions, therebycausing future reworking in the designing process. For instance, if anHDL description is formed of a plurality of hierarchical levels, thecase is often encountered where a terminal definition description ineach level and a terminal description in an instance disagree. Thisdisagreement is sometimes caused by mistake, and might sometimes beinsignificant at all in terms of grammar and circuit expression. In themeantime, since a possibility cannot be eliminated that the disagreementwould result in a future problem in circuit expression, thereby causingsome reworking in a later stage, a technique has ever been longed forautomatically removing the disagreement.

[0015] Furthermore, at describing a circuit design in an HDL, anoriginally employed HDL is often converted into another HDL (hereinaftercalled “the latter HDL”), for the purpose of establishing aninter-system linkage or due to some reasons raised in a design flow. Atthat time, there sometimes occurs a case where an HDL description thatmeets language rules of the current HDL would not comply with languagerules of the latter HDL. In view of the probability, it has ever beenlonged that the original HDL description is allowed to be automaticallymodified in advance into a description that complies with the languagerules of not only the current HDL but also the latter HDL, in order toprevent prospected defects in the circuit design.

[0016] And further, in an HDL description that is to be subjected tologic synthesis, there often remains a waveform observation-dedicatedsimulation description, which has been used at logic verification and isincapable of logic synthesis, without being annotated. Since it has longbeen impossible to automatically modify (delete) this type of logicsynthesis-incapable description, the description had to be manuallymodified by a designer at its detection, and any action could not betaken unless an error is actually caused in a logic synthesis tool dueto such a logic synthesis-incapable description.

SUMMARY OF THE INVENTION

[0017] With the foregoing problems in view, objects of the presentinvention are to automatically modify serious semantic grammar errorsand to clearly indicate the modified portions. Further objects of thepresent invention are to automatically modify the portions which are notgrammar errors but should be considered in view of circuit designing andto clearly indicate the modified portions. As a result, burdens ondesigners would be significantly reduced and high-quality HDLdescriptions would be obtained.

[0018] In order to accomplish the above objects, according to thepresent invention, there is provided an apparatus for automaticallymodifying an HDL description (circuit design information) described in aHDL, which apparatus comprises: HDL lexical analysis means forperforming a lexical analysis of the HDL description which is to bemodified; HDL syntax analysis means for performing a syntax analysis ofthe HDL description based on the result of the lexical analysis by theHDL lexical analysis means, to convert the HDL description into a parsetree format description; semantic grammar error detection means forperforming semantic analysis of the HDL description based on the resultof the syntax analysis by the HDL syntax analysis means, detecting aportion of the HDL description, in which portion variables on right andleft sides of an assignment statement are inconsistent in type, andregarding the detected portion as a semantic-grammar-error portion; atype conversion template for defining a type conversion function, whichconverts the type of the variable on the right side of the assignmentstatement into that of the variable on the left side of the assignmentstatement, as a type conversion rule; semantic grammar error modifyingmeans for modifying the semantic-grammar-error portion into a correctdescription by applying the type conversion function, which has beendefined by the type conversion template, to the right side of theassignment statement which side has been regarded as thesemantic-grammar-error portion by the semantic grammar error detectingmeans; HDL reverse syntax analysis means for performing a reverse syntaxanalysis of the HDL description, which has been modified by the semanticgrammar error modifying means, to convert the HDL description from theparse tree format description into an ordinary format description; andcomment attaching means for attaching a comment about the modificationto the modified portion, which is the portion as the result of themodification by the semantic grammar error modifying means.

[0019] As one preferred feature, the apparatus further comprises: acontrol information template for defining a to-be-modified item (hereinafter called “object item”), which is not a grammar error but should beconsidered in view of circuit designing, and a modification rule tomodify the object item; object item detecting means for detecting aportion corresponding to the object item in the HDL description, basedon the result of the syntax analysis by the HDL syntax analysis means;and object item modifying means for modifying the last-namedcorresponding portion, which has been detected by the object itemdetecting means, in accordance with the modification rule defined by thecontrol information template. The HDL reverse syntax analysis means isoperable to perform a reverse syntax analysis of the modified HDLdescription, which is the description as the result of the modificationby the semantic grammar error modifying means and the object itemmodifying means, and the comment attaching means is operable to attach acomment about the modification to the modified corresponding portion,which is the portion as the result of the modification by the semanticgrammar error modifying means and the object item modifying means.

[0020] As one generic feature, the present invention provides anapparatus for automatically modifying an HDL description described in anHDL, which apparatus comprises: in addition to the above-described HDLlexical analysis means and HDL syntax analysis means, a controlinformation template for defining a to-be-modified item (hereinaftercalled “object item”), which is not a grammar error but should beconsidered in view of circuit designing, and a modification rule tomodify the object item; object item detecting means for detecting aportion corresponding to the object item in the HDL description, basedon the result of the syntax analysis by the HDL syntax analysis means;object item modifying means for modifying the last-named correspondingportion, which has been detected by the object item detecting means, inaccordance with the modification rule defined by the control informationtemplate; HDL reverse syntax analysis means for performing reversesyntax analysis of the modified HDL description, which is thedescription as the result of the modification by the object itemmodifying means, to convert the HDL description from the parse treeformat description into an ordinary description; and comment attachingmeans for attaching a comment about the modification to the modifiedcorresponding portion, which is the portion as the result of themodification by the object item modifying means.

[0021] As another generic feature, the present invention provides acomputer-readable recording medium in which a program for automaticallymodifying an HDL description described in an HDL is recorded, whereinthe program instructs a computer to function as the above-described HDLlexical analysis means, HDL syntax analysis means, object item detectingmeans, object item modifying means, HDL reverse syntax analysis means,and comment attaching means.

[0022] The automated HDL modifying apparatus and the computer-readablerecording medium in which a program for automatically modifying HDL isrecorded, according to the present invention, guarantee the followingadvantageous results.

[0023] (1) Since serious semantic grammar errors are automaticallymodified and the modified portions are clearly shown, it is possible tosignificantly reduce burdens on designers, and also possible to obtain ahigh-quality HDL description.

[0024] (2) Partly since a portion which is not a grammar error butshould be considered in view of circuit designing is automaticallymodified into an appropriate description, and partly since the modifiedportion is clearly shown, it is possible to significantly reduce burdenson designers, and also possible to obtain a high-quality HDLdescription.

[0025] (3) By appropriately defining object items and modification rulesin a control information template, it is possible to detect andautomatically modify, in an early stage, a portion (in appropriatedescription) which should be considered in view of circuit designing andcareless mistakes made by designers, thereby surely preventing theoccurrence of reworking in the designing process.

[0026] (4) A modification comment is attached to the modified portion,making it possible for a designer to visually recognize where and inwhat way the modification has been performed. It is thus also possiblefor the designer to check, with ease and certainty, whether or not theresult of the automatic modification complies with the designer'sintention, and thereby burdens on the designer are significantlyreduced.

[0027] (5) Such a modification comment attached to the modified portioninforms the designer about in what situations he/she is apt to makemodification-required descriptions, thereby exerting educationaleffects.

[0028] (6) By appropriately defining object items and modification rulesin a control information template, it is possible, with considerationgiven to a possibility that a current HDL description being modified isconverted into another HDL, to automatically modify the HDL descriptionin advance so as to comply with language rules of not only the currentHDL but also the latter HDL, thereby preventing the occurrence ofcircuit designing-relevant problems even after the conversion performed.Accordingly, it is possible to obtain a HDL description that would causeno problems in circuit designing even if employed in more than one HDL,without placing any burdens on designers.

[0029] (7) By appropriately defining object items and modification rulesin a control information template, it is possible to automaticallymodify a character string that contains any prohibited character thereininto a new character string that neither is contained in the HDLdescription nor includes any predetermined prohibited characters.Accordingly, even if two or more designers are involved in generatingthe HDL description, resulting in various violations of the namingrules, it is still possible to modify the names (character string) thatare against the naming rules, with ease and certainty, thereby obtaininga modified HDL description that obeys the naming rules.

[0030] (8) By appropriately defining object items and modification rulesin a control information template, it is possible to automaticallymodify terminal descriptions which are inconsistent between a pluralityof hierarchical levels of the HDL description, into descriptions whichare consistent between all of the plural hierarchical levels of the HDLdescription. Accordingly, it is thoroughly possible, in an early stage,to detect and automatically modify such inappropriate descriptions,which so far have been detected not by the front-end (languageprocessor) but by the back-end (logic synthesis tool or verificationtool), thereby surely preventing the occurrence of reworking in thedesigning process.

[0031] (9) By appropriately defining object items and modification rulesin a control information template, it is possible to automaticallymodify a portion in which the relationship between the left side and theright side of a signal assignment description is incorrect, into acorrect relationship.

[0032] (10) By appropriately defining object items and modificationrules in a control information template, it is possible to automaticallydelete a portion in an HDL description whose synthesis is unavailable bya logic synthesis tool, or to add/write-in a directive for instructingthe logic synthesis tool to ignore the portion. Hereby, even if alogic-synthesis-incapable waveform observation-dedicated simulationdescription, which has been used at the logic verification, remains inthe HDL description without being annotated, there would be caused noproblems (errors) in a logic synthesis tool. Accordingly, it is nolonger necessary for designers to delete such synthesis-incapabledescriptions by manual operation, thereby significantly reducing burdenson the designers.

[0033] Other objects and further features of the present invention willbe apparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is a block diagram schematically showing an automated HDLmodifying apparatus of one embodiment of the present invention; and

[0035]FIG. 2 through FIG. 9 are diagrams each illustrating operations ofthe automated HDL modifying apparatus of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0036] One preferred embodiment of the present invention will now bedescribed in detail with reference to relevant accompanying drawings.

[0037] [1] Construction of One Embodiment:

[0038]FIG. 1 depicts an automated HDL modifying apparatus of oneembodiment of the present invention. Referring to FIG. 1, the presentembodiment of automated HDL modifying apparatus 1, which modifies an HDLdescription (circuit design information described in HDL) in anautomatic way, is shown to include HDL lexical analysis means 11, HDLsyntax analysis means 12, syntactic grammar error detection means 13,syntactic grammar error modifying means 14, semantic grammar errordetection means 15, semantic grammar error modifying means 16, objectitem detecting means 17, object item modifying means 18, HDL reversesyntax analysis means 19, comment attaching means 20, databases 21through 24, and templates 30, 40, and 51 through 55.

[0039] HDL lexical analysis means 11 performs lexical analysis of HDLdescription (original HDL description) 2A which is to be modified:namely, parsing to-be-modified HDL description 2A into basic units ofcharacter string, or tokens, and writing the individual basic units,together with the information of their types, in token database 21.

[0040] HDL syntax analysis means 12, based on the tokens (the result ofthe analysis by HDL lexical analysis means 11) stored in token database21, performs syntax analysis of HDL description 2A to convert into aparse tree format description.

[0041] Grammar analysis template 30 defines various rules: rulesdefining the use of reserved words; rules for spelling; and rules forsyntax. Here, “syntax rules” mean syntactic grammar rules such as that asemicolon “;” should be written at the end of a statement that includesa “=” therein.

[0042] Syntactic grammar error detection means 13 detects syntacticgrammar errors (incorrect spellings, statements that contain a “=” butwith no “;” placed at their ends, reserved words incorrectly used, andothers) based on grammar analysis template 30 and the result of theanalysis by HDL syntax analysis means 12. Syntactic grammar errormodifying means 14 modifies the syntactic grammar error, which has beendetected by syntactic grammar error detection means 13, into a correctdescription in accordance with the rules defined by grammar analysistemplate 30.

[0043] The resulting modified description by syntactic grammar errormodifying means 14 is written in HDL database 22. In this instance, ifno syntactic grammar error is detected by syntactic grammar errordetection means 13, the result of the analysis by HDL syntax analysismeans 12 is written in HDL database 22 directly without undergoing themodification by syntactic grammar error modifying means 14.

[0044] Semantic grammar error detection means 15 performs semanticanalysis of HDL description 2A based on the data (the result of theanalysis by HDL syntax analysis means 12 or the result of themodification by syntactic grammar error modifying means 14) stored inHDL database 22, and detects a portion of the HDL description, in whichportion variables on the right and the left sides of an assignmentstatement are inconsistent in type, as a semantic-grammar-error portion.

[0045] Type conversion template 40 defines a type conversion function,which converts the type of a variable on the right side of an assignmentstatement into that of a variable on the left side of the assignmentstatement, as a type conversion rule. The type conversion function willbe described in detail later, making reference to Table 1.

[0046] Semantic grammar error modifying means 16 modifies thesemantic-grammar-error portion into a correct description by applyingthe type conversion function, which has been defined by the typeconversion template 40, to the right side of the assignment statementwhich side has been regarded as the semantic-grammar-error portion bythe semantic grammar error detection means 15. The resulting modifieddescription is written in HDL database 23. Concrete modifying operationsby automated HDL modifying apparatus 1 of the present embodiment will bedescribed in detail later with reference to FIG. 2.

[0047] In this instance, if no semantic grammar error is detected bysemantic grammar error detection means 15, semantic grammar errormodifying means 16 performs no modification, and HDL database 23, as itis, serves as HDL database 23.

[0048] Templates (or control information templates) 51 through 55 definevarious types of to-be-modified items (hereinafter called “objectitem”), which are not grammar errors but should be considered in view ofcircuit designing, and modification rules for modifying the objectitems.

[0049] Object item detecting means 17 detects a portion corresponding toany one of the object items, which are defined by templates 51 through55, in the HDL description 2A, based on the data (the result of theanalysis by the HDL syntax analysis means 12 or the result of themodification by syntactic grammar error modifying means 14/semanticgrammar error modifying means 16) stored in HDL database 23.

[0050] Object item modifying means 18 modifies the portion, which hasbeen detected by object item detecting means 17, in accordance with themodification rules defined by templates 51 through 55. The resultingmodified description is written in HDL database 24.

[0051] At that time, if no portion is detected that corresponds to anyof the object items by object item detecting means 17, object itemmodifying means 18 performs no modification, and HDL database 23, as itis, serves as HDL database 24.

[0052] HDL reverse syntax analysis means 19 performs reverse syntaxanalysis of the data stored in HDL database 24, or the HDL description(a parse tree format description) which has been modified by syntacticgrammar error modifying means 14, semantic grammar error modifying means16, and object item modifying means 18, to convert the HDL descriptionfrom the parse tree format description into an ordinary formatdescription. The resulting converted description is output as modifiedHDL description 2B.

[0053] Comment attaching means 20 attaches a comment about themodification to the corresponding modified portion (the portion as theresult of the modification by the syntactic grammar error modifyingmeans 14, semantic grammar error modifying means 16, and object itemmodifying means 18). A concrete description of such comments that areattached to HDL description 2B will be described later, making referencewith FIG. 2 through FIG. 9. Here, if automated HDL modifying apparatus 1makes no modification to original HDL description 2A, comment attachingmeans 20, as a matter of course, attaches no comment to modified HDLdescription 2B, either. In the meantime, comment attaching means 20 alsoattaches a comment to modified HDL description 2B (source) output fromHDL reverse syntax analysis means 19.

[0054] Hereinbelow, templates 51 through 55 will now be described inmore details.

[0055] Object items to be modified are defined in language conversionrule template 51 in such a manner that, on the assumption that the HDL(say, VHDL) being currently modified is converted into another HDL (say,Verilog-HDL), object item detecting means 17 detects a portion of thecurrent HDL description, which portion, after being converted, would notcomply with language rules of the latter HDL, as a portion correspondingto the object item. Modification rules are defined in languageconversion rule template 51 in such a manner that object item modifyingmeans 18 modifies the last-specified corresponding portion, which hasbeen detected by object item detecting means 17, into a correctdescription that would comply with language rules of the latter HDLafter the conversion.

[0056] Referring now to FIG. 3, language conversion rule template 51includes reserved word template 51 a, name template 51 b, namegeneration rule 51 c, and upper/lower cases rule 51 d. Reserved wordstemplate 51 a registers/defines reserved words that are available foreach HDL, and name template 51 b registers/defines terminal names andnet names that are available for each HDL. Name generation rule 51 cdefines rules for generating a new character string, which is unique andnot contained in the HDL description, as a new terminal name or a newnet name. Further, upper/lower cases rule 51 d registers/defines whetheror not each HDL is case-sensitive.

[0057] As described later with reference to FIG. 3, using reserved wordstemplate 51 a and name template 51 b, for example, if there is detectedin a Verilog-HDL description a character string that is available as aterminal name or a net name in Verilog-HDL but is available as areserved word in VHDL, the character string is converted/modified intoanother new character string that is not defined as a reserved word. Atthat time, in accordance with name generation rule 51 c, a uniquecharacter string that is not contained in the HDL description isgenerated as the new character string.

[0058] If the current HDL, now being modified, is found to becase-sensitive (Verilog-HDL, for example) in accordance with upper/lowercases rule 51 d (see FIG. 3), language conversion rule template 51defines the object item in such a manner that, in consideration of apossibility that the current HDL might be converted into another HDLthat is case-insensitive, object item detecting means 17 detects one ofa pair of character strings which are composed of common charactersarranged in the same order and described case-sensitively, as a portioncorresponding to the object item. At that time, language conversion ruletemplate 51 defines modification rules in such a manner that object itemmodifying means 18, in accordance with name generation rule 51 c,generates a new character string that is not contained in the HDLdescription, and then replaces the above-mentioned one of the twocharacter strings, which has been detected by the object item detectingmeans, with the thus generated new character string.

[0059] Otherwise if the current HDL is found to be case-insensitive(VHDL, for example) in accordance with upper/lower cases rule 51 d (seeFIG. 3), in consideration of a possibility that the current HDL might beconverted into another HDL that is case-sensitive, language conversionrule template 51 defines the object item in such a manner that theobject item detecting means 17 detects every upper case character orevery lower case character in character strings in the HDL description,as a portion corresponding to the object item. At that time, languageconversion rule template 51 defines modification rules in such a mannerthat object item modifying means 18 converts every upper case characterinto a lower case character, or every lower case character into an uppercase character.

[0060] Concrete modifying operations with use of language conversionrule template 51 will be described in detail later with reference toFIG. 3.

[0061] Prohibited character information template 52 defines the objectitem in such a manner that the object item detecting means 17 detects acharacter string which includes any predetermined prohibited character,as a portion corresponding to the object item. Further, prohibitedcharacter information template 52 defines modification rules in such amanner that the object item modifying means 18 generates a new characterstring which neither is contained in the HDL description nor includesany predetermined prohibited character, and then replaces theprohibited-character-included character string, which has been detectedby the object item detecting means 17, with the thus generated newcharacter string.

[0062] Referring now to FIG. 4, prohibited character informationtemplate 52 has prohibited character template 52 a and name generationrule 52 b. Prohibited character template 52 a defines/registersunavailable character strings, and object item detecting means 17detects a character string that contains any of the unavailablecharacters, making reference to prohibited character template 52 a, as aportion corresponding to the object item. Name generation rule 52 b,which is similar to name generation rule 51 c, defines rules forgenerating a new, unique character string which neither is not containedin the HDL description nor includes any of the predetermined prohibitedcharacters, and in accordance with this name generation rule 52 b,object item modifying means 18 generates the above-mentioned newcharacter string.

[0063] Concrete modifying operations with use of prohibited characterinformation template 52 will be described in detail later with referenceto FIG. 4.

[0064] Hierarchy information template 53 defines the object item to bemodified in such a manner that object item detecting means 17 detects aportion of the HDL description, which portion is inconsistent interminal description between a plurality of hierarchical levels of theHDL description, as a portion corresponding to the object item. Further,hierarchy information template 53 defines modification rules in such amanner that object item modifying means 18 modifies the inconsistentterminal description in the above-mentioned corresponding portion, whichhas been detected by object item detecting means 17, into a correctdescription which is consistent between all of the plural hierarchicallevels of the HDL description.

[0065] Concrete modifying operations with use of hierarchy informationtemplate 53 will be described in detail later with reference to FIG. 5through FIG. 8. Further, hierarchy information template 53 hasmodification rules 53 a through 53 d as shown in FIG. 5 through FIG. 8,respectively. Such modification rules 53 a through 53 d will bedescribed later in detail.

[0066] Connection information template 54 defines the object item insuch a manner that object item detecting means 17 detects a portion ofthe HDL description, which portion yields an incorrect relationshipbetween the left and the right sides of a signal assignment description,as a portion corresponding to the object item. Further, connectioninformation template 54 defines modification rules in such a manner thatobject item modifying means 18 modifies the above-mentionedcorresponding portion, which has been detected by object item detectingmeans 17, into a correct description which yields a correct relationshipbetween the left and the right sides of the signal assignmentdescription. Concrete modifying operations with use of connectioninformation template 54 will be described later in detail.

[0067] Synthesis-incapable description template 55 defines the objectitem in such a manner that object item detecting means 17 detects aportion (synthesis-incapable portion) in the HDL description, whichportion is unable to be synthesized by a logic synthesis tool, as aportion corresponding to the object item. Further, synthesis-incapabledescription template 55 defines modification rules in such a manner thatthe object item modifying means 18 deletes the above-mentionedcorresponding portion, which has been detected by the object itemdetecting means 17, or that the object item modifying means 18 adds tothe corresponding portion, which has been detected by the object itemdetecting means 17, a directive for instructing the logic synthesis toolto ignore the corresponding portion. The selection between the above twotypes of modification rules depends upon a designer.

[0068] Concrete modifying operations with use of synthesis-incapabledescription template 55 will be described in detail later with referenceto FIG. 9. Synthesis-incapable description template 55 has modificationrule 55 a of FIG. 9. As to modification rule 55 a, a detaileddescription will be given later, and modification rule 55 a of FIG. 9 isdefined in such a manner that a directive is added/written in.

[0069] HDL lexical analysis means 11, HDL syntax analysis means 12,syntactic grammar error detection means 13, syntactic grammar errormodifying means 14, semantic grammar error detection means 15, semanticgrammar error modifying means 16, object item detecting means 17, objectitem modifying means 18, HDL reverse syntax analysis means 19, andcomment attaching means 20 each can be realized by dedicated software(automated HDL modification program).

[0070] This automated HDL modification program is provided in the formof being recorded in a computer-readable recording medium such as aflexible disc and a CD-ROM. Also, in user, automated HDL modifyingapparatus 1 can be realized as a computer (not shown) constituted by aCPU, a ROM, a RAM, and soon. The ROM stores the automated HDLmodification program having been previously recorded therein, and theCPU reads out and executes the program, thereby realizing the functionsof the above-described various means 11 through 20.

[0071] In the meantime, the automated HDL modification program could bestored alternatively in a storage device (recording medium) such as amagnetic disc, an optical disc, a magneto-optical disc, and others, soas to be transferred from such a storage device to the computer via acommunication path.

[0072] Further, information defined in templates 30, 40, and 51 through55, could be input manually by a designer through a keyboard, a mouse,and others. Or else, it could be input by way of a recording medium,separately, or it could also be provided as part of the automated HDLmodification program.

[0073] Furthermore, aforementioned HDL databases 21 through 24 can berealized by either of the RAM or the recording medium such as a flexibledisc, a CD-R, and a CD-RW.

[0074] [2] Operation of One Embodiment:

[0075] Next, a description of an operation of automated HDL modifyingapparatus 1 of the present embodiment, being constructed as above, willnow be given in more details.

[0076] Firstly, here will be briefly described a sequence of automatedmodification operations executed by automated HDL modifying apparatus 1of the present embodiment.

[0077] After being input to automated HDL modifying apparatus 1, HDLdescription (original HDL description) 2A which is to be modified isparsed into basic units of character string, or tokens, by the HDLlexical analysis means 11, and the tokens are then written in tokendatabase 21.

[0078] On the basis of the tokens, HDL syntax analysis means 12 performssyntax analysis of HDL description 2A to convert it into a parse treeformat description. Syntactic grammar error detection means 13, based onthe resulting parse tree and grammar analysis template 30, detectssyntactic grammar errors. If any syntactic grammar error is detected,syntactic grammar error modifying means 14 modifies the error into acorrect description in accordance with the rules defined by grammaranalysis template 30. The resulting modified description is written inHDL database 22.

[0079] The HDL description 2A, whose syntactic grammar errors havealready been modified as above, is then subjected to semantic analysisby semantic grammar error detection means 15 based on the data stored inHDL database 22, and a portion of the HDL description, in which portionvariables on the right and the left sides of an assignment statement areinconsistent in type, is resultantly detected as asemantic-grammar-error portion. If any semantic-grammar-error portion isdetected, semantic grammar error modifying means 16 applies a typeconversion function, which is defined by the type conversion template40, to the right side of the assignment statement which side has beenregarded as the semantic-grammar-error portion, and hereby the semanticgrammar error is modified into a correct description, and the resultingmodified description is written in HDL database 23.

[0080] Further, object item detecting means 17 detects in the HDLdescription 2A, whose semantic grammar errors have already been modifiedas above, portions corresponding to any of the object items that aredefined by templates 51 through 55. Upon detection of such portions, ifany, object item modifying means 18 modifies the portions in accordancewith modification rules defined by templates 51 through 55. Theresulting modified descriptions are written in HDL database 24.

[0081] The parse tree format HDL description, which has undergone thevarious types of modifications, is then converted into an ordinaryformat description by HDL reverse syntax analysis means 19, and outputas modified HDL description 2B. Every modified portion in modified HDLdescription 2B has a comment about its modification attached thereto bycomment attaching means 20.

[0082] Secondly, referring now to FIG. 2 through FIG. 9, a descriptionwill now be made hereinbelow of automated modification operations thatautomated HDL modifying apparatus 1 of the present embodiment executesupon an HDL description described in VHDL or Verilog-HDL. Here will begiven concrete descriptions of semantic grammar errors, to-be-modifieditems (hereinafter called “object items”), modification operations formodifying the items, and comments attached to the modification results;these are all features of the present embodiment.

[0083] [2-1] Operations for Modifying Semantic Grammar Errors:

[0084] In some HDLs, say, VHDL, variables inconsistent in type betweenthe right side and the left side of an assignment statement, areregarded as grammar errors. According to the present embodiment, upondetection of such a semantic grammar error by semantic grammar errordetection means 15, semantic grammar error modifying means 16automatically modifies the error using type conversion template 40, andthe specification of the modification is attached/written-in, as acomment, to the modified portion in a source (modified HDL description2B) by comment attaching means 20.

[0085] For example, referring to HDL description 2A (described in VHDL)of FIG. 2, the type of an input variable “a” (right side) is“std_ulogic”, while the type of an output variable “b” (left side) is“bit”. Since the type of the variable on the right side differs fromthat of the variable on the left side, a portion “b<=a;” in original HDLdescription 2A is detected as a semantic grammar error. Thistype-inconsistent portion is detected by semantic grammar errordetection means 15 while it is searching HDL database 22.

[0086] Semantic grammar error modifying means 16 evaluates whether ornot type conversion template 40 has a type conversion pattern (typeconversion rule, type conversion function) that is required formodifying the type-inconsistent portion. Here, in type conversiontemplate 40, the type conversion pattern (type conversion rule)“To_bit”, which is for use in case where the variable type on the leftside is “bit” while that on the right side is “std_ulogic”, isprovided/defined by a library “std _logic_(—)1164”.

[0087] Accordingly, the semantic grammar error portion “b<=a;” isautomatically converted by semantic grammar error modifying means 16into “b<=To_bit(a);” in modified HDL description 2B. Additionally,comment attaching means 20 puts a comment “--TYPE CONVERTED” after theresulting modified portion “b<=To_bit(a);”.

[0088] In this instance, type conversion template 40 defines typicaltype conversion patterns (type conversion rule, type conversionfunction) previously. Representative examples of such type conversionpatterns are shown in the following Table 1. Further, a librarystatement and a use statement, which are for use in referring to alibrary and a package where a type conversion function is stored, couldbe automatically added, if necessary. TABLE 1 LEFT SIDE RIGHT SIDELIBRARY PACKAGE bit std_ulogic std_logic_1164 To_bit bit_vectorstd_logic_(—) std_logic_1164 To_bitvector vector std_ulogic_(—)std_logic_1164 To_bitvector vector std_ulogic bit std_logic_1164To_StdULogic std_ulogic_(—) std_logic_(—) std_logic_1164To_StdULogicVector vector vector bit_vector std_logic_1164To_StdULogicVector std_logic_(—) bit_vector std_logic_1164To_StdLogicVector vector std_ulogic_(—) std_logic_1164 To_StdLogicVectorvector integer std_logic_arith CONV_STD_(—) LOGIC_VECTOR unsignedstd_logic_arith CONV_STD_(—) LOGIC_VECTOR signed std_logic_arithCONV_STD_(—) LOGIC_VECTOR std_ulogic std_logic_arith CONV_STD_(—)LOGIC_VECTOR boolean std ulogic std_logic_1164 is_X std_logic_(—)std_logic_1164 is_X vector std_ulogic_(—) std_logic_1164 is_X vectornatural unsigned numeric_std TO_INTEGER integer signed numeric_stdTO_INTEGER std_logic_(—) std_logic_signed CONV_INTEGER vector unsignedstd_logic_arith CONV_INTEGER signed std_logic_arith CONV_INTEGERstd_ulogic std_logic_arith CONV_INTEGER unsigned natural numeric_stdTO_UNSIGNED integer std_logic_arith CONV_UNSIGNED signed std_logic_arithCONV_UNSIGNED std_ulogic std_logic_arith CONV_UNSIGNED signed natualnumeric_std TO_SIGNED integer std_logic_arith CONV_SIGNED unsignedstd_logic_arith CONV_SIGNED std_ulogic Std_logic_arith CONV_SIGNED

[0089] [2-2] Modification Operation with Language Conversion RuleTemplate:

[0090] In an HDL-used circuit designing, an initially used HDL is oftenconverted into another HDL (hereinafter called “the latter HDL”), forthe purpose of establishing an inter-system linkage or due to somereasons raised in a design flow. At that time, there sometimes occurs acase where an HDL description that meets language rules of the currentHDL would not comply with language rules of the latter HDL. In view ofsuch a probability (on the assumption of grammar errors caused after theHDL conversion), automated HDL modifying apparatus 1 of the presentembodiment automatically modifies the current HDL description in advanceinto a description that complies with the language rules of the latterHDL so as to prevent any defects in circuit designing (grammar errorsafter the HDL conversion).

[0091] In other words, though some tools for converting an HDL intoanother HDL have already been provided in the market, the presentembodiment executes no such HDL conversion actually, but checks thelanguage rules of the latter HDL with consideration given to aprospective conversion of the current HDL into the latter HDL, and thencarries out automatic modifications according to the check results. Inthis manner, since the language rules of the latter HDL are previouslychecked, it is possible to obtain HDL description 2B that would cause noproblems in circuit designing even if employed in more than one HDL,without placing any burdens on designers. Accordingly, it is alsopossible to convert an HDL into another HDL at anytime, and even afterthe conversion carried out, it would no longer necessary to correcterrors.

[0092] Referring now to FIG. 3, object item detecting means 17 ofautomated HDL modifying apparatus 1 of the present embodiment reads-inreserved words template 51 a, name template 51 b, upper/lower cases rule51 d, each of which is included in language conversion rule template 51,and detects a portion which does not meet the template 51 a, 51 b, orupper/lower cases rule 51 d. The detected error portion is convertedinto a newly generated description (character string) that has beenautomatically generated according to name generation rule 51 c. Further,not only such language rule errors prospected after the languageconversion but also confusing descriptions are detected andautomatically modified.

[0093] For example, HDL description 2A described in Verilog-HDL ischecked by syntactic grammar error detection means 13 for Verilog-HDLreserved words, and also is checked by object item detecting means 17for reserved words for another HDL, say, VHDL, using reserved wordstemplate 51 a and name template 51 b. At that time, reserved wordstemplate 51 a defines/registers all the reserved words for all the HDLsinto which the conversion is likely to be performed, and name template51 b registers/defines terminal names and net names available for theindividual HDLs.

[0094] Referring now to HDL description 2A of FIG. 3, which is describedin Verilog-HDL, “in” and “out” are used as a terminal name or a netname. Meanwhile, these are reserved words in VHDL, thus prohibited frombeing used as a terminal name or a net name. In this manner, if thedescriptions “in” and “out”, which would cause errors after beingconverted into another HDL, are detected by object item detecting means17 as to-be-modified (object) portions, object item modifying means 18reads-in name generation rule 51 c, in which suffixes, prefixes,connectives, and serial numbers are recorded, and automaticallygenerates new descriptions “in_(—)1” and “out_(—)1” according to therule 51 c, as new character strings (names).

[0095] Each of the thus generated “in_(—)1” and “out_(—)1” is a uniquecharacter string that is not contained in HDL description 2A, and isavailable as a terminal name or a net name in both Verilog-HDL and VHDL.

[0096] The “in” and “out” are automatically replaced with “in_(—)1” and“out_(—)1”, respectively, in modified HDL description 2B, and there isadded a comment “//CORRECTED” at the end of the modified line by commentattaching means 20.

[0097] Further, in HDL description 2A described in Verilog-HDL, the useof an “a_(——)b” (see FIG. 3) or a “$” as a part of the characterscomposing a net name agrees with language rules of Verilog-HDL,meanwhile it disagrees with language rules of VHDL. If such an HDLdescription 2A is converted from Verilog-HDL into VHDL, an error islikely to be caused, and thus object item modifying means 18automatically generates a unique character string (name), as similar tothe above-mentioned ones, and replaces the prospected error portion withthe automatically generated name.

[0098] In FIG. 3, a character string “a_(——)b” in HDL description 2A isautomatically replaced with “a_b” in modified HDL description 2B, andalso, at the end of the modified line a modification comment“//CORRECTED” is added by comment attaching means 20.

[0099] Furthermore, note that Verilog-HDL is case-sensitive, while VHDLis case-insensitive. If HDL description 2A described in Verilog-HDL,being composed of both upper case characters and lower case characters,is converted into VHDL, there would be caused confusion. That is, an “a”is distinguished from an “A” in HDL description 2A of FIG. 3, while VHDLmakes no distinction between an “a” and “A”, thus causing confusion.

[0100] Accordingly, in automated HDL modifying apparatus 1, withconsideration given to the possibility that Verilog-HDL is convertedinto VHDL, object item detecting means 17 detects either one (“A” inthis example) of the character strings “A” and “a”, which are composedof a common character and described case-sensitively, as an object itemto be modified, and object item modifying means 18 automaticallygenerates a unique character string (name) “A_(—)1” according to namegeneration rule 51 c. The newly generated character string is a uniqueone that does not overlap any existing character string in the HDLdescription.

[0101] After that, each character “A” in HDL description 2A is replacedwith a character string “A_(—)1” in modified HDL description 2B, and atthe end of the modified line, comment attaching means 20 attaches amodification comment “//CORRECTED”. In this manner, each “A” is replacedwith an “A_(—)1”, thereby made distinguishable from the name “a” notonly in Verilog-HDL but also in VHDL.

[0102] On the contrary, at checking an HDL description described inVHDL, which is case-insensitive, with consideration given to apossibility that the description is converted into Verilog-VHDL, whichis case-sensitive, object item detecting means 17 detects every uppercase character or every lower case character in character strings, as aportion corresponding to an object item to be modified, and object itemmodifying means 18 automatically converts every upper case characterinto a lower case character, or every lower case character into an uppercase character. In other words, after the modification performed, allthe characters in the HDL description described in VHDL are either inuppercase only or in lowercase only.

[0103] In VHDL, for example, a terminal name “b” is regarded as the sameas a terminal name “B”, while in Verilog-HDL, these are regarded as thetwo different terminal names, hereby often causing confusion. Inautomated HDL modifying apparatus 1 of the present embodiment, however,HDL description 2A in VHDL is written either in uppercase only or inlowercase only, and the above “b” and “B” are uniformed into either oneof them, thereby preventing such confusion.

[0104] [2-3] Modification Operation with Prohibited Character Template:

[0105] At circuit designing in an HDL, there is often a case where twoor more designers are involved or where some tools are employed. In sucha design, name rules become often inconsistent throughout the HDLdescription. For this reason, in view of an interface between the toolsand a prospective conversion into another HDL, the names have beenuniformed manually.

[0106] Meanwhile, object item detecting means 17 of automated HDLmodifying apparatus 1, as shown in FIG. 4, reads-in prohibited charactertemplate 52 a included in prohibited character information template 52,and using the prohibited character template 52 a, object item detectingmeans 17 checks HDL description 2A for prohibited characters. If anyprohibited character is found to be used in module names, externalterminal names, instance names, net names, type names, component names,aliases for external terminals, or others, the character string (name)that includes any prohibited character is converted into a new name(character string) which is generated according to name generation rule52 b.

[0107] Referring now to FIG. 4, using prohibited character template 52 athat registers prohibited characters of “$” and “&”, object itemdetecting means 17 checks HDL description 2A described in Verilog-HDLfor these prohibited characters “$” and “&”. At that time, in theexample of FIG. 4, a character “$”, which is used as an instance name,is detected as an object item to be modified, and object item modifyingmeans 18 generates a new character string (name), say, “X1”, whichneither is contained in to-be-modified HDL description 2A nor includesany predetermined prohibited character, in accordance with namegeneration rule 52 b (here, “prefix:X;”)

[0108] The character “$” in HDL description 2A is automatically replacedwith the new character string “X1” in modified HDL description 2B, andat the end of the statement, comment attaching means 20 attaches amodification comment “//CORRECTED”.

[0109] Hereby, even if two or more designers generate HDL description2A, making various violations of the naming rules, it is still possibleto correct the names (character strings) which are against the namingrules, with ease and certainty, thereby obtaining modified HDLdescription 2B that obeys the naming rules.

[0110] [2-4] Modification Operation with Hierarchy Information Template:

[0111] In HDL description 2A having a multi-level hierarchical structure(see FIG. 5, for example), there is often a case where an inconsistency(disagreement) is found between a terminal definition description ineach hierarchy and a terminal description of an instance. Suchinconsistencies in terminal descriptions are caused sometimes due togrammar errors made by designers, or sometimes due to descriptions whichare not grammar errors but inappropriate as circuit descriptions. Inthese cases, the inconsistencies are preferred to be resolved.

[0112] Further, since Verilog-HDL is a type of language in which someterminal descriptions are optional, the above inconsistencies in theterminal descriptions are usually seen in an HDL description describedin Verilog-HDL. Although such inconsistencies are not defects or errorsin circuit descriptions, it is preferred, for purpose of safety, thatthe description is as clear as possible with no such inconsistencies.

[0113] Accordingly, in automated HDL modifying apparatus 1 of thepresent embodiment, the following rules are defined as modificationrules 53 a through 53 d, respectively, of hierarchy information template53:

[0114] (1) all the module port names (terminal names) are to be recitedin each instance (see FIG. 5);

[0115] (2) a bit width description in an upper level hierarchy is to bematched with that in an lower level hierarchy (see FIG. 6);

[0116] (3) a component port description in an upper level hierarchy isto be matched with that in an lower level hierarchy (see FIG. 7); and

[0117] (4) port names (terminal names) in instances are to be describedin an uniform fashion: a name-adapted fashion or a position-adaptedfashion (see FIG. 8).

[0118] In accordance with these modification rules 53 a through 53 d,object item detecting means 17 detects a portion of the HDL description,which portion is inconsistent in terminal description (port namedescription) between a plurality of hierarchical levels of the HDLdescription, as a portion corresponding to an object item to bemodified. Object item modifying means 18 then modifies the terminaldescription in the detected portion into a description that isconsistent between all of the plural hierarchical levels of the HDLdescription, according to the control information (hierarchy informationtemplate 53) that defines language grammar and modification rules 53 athrough 53 d.

[0119] In HDL description 2A described in Verilog-HDL with ahierarchical structure, it is not necessary to recite unassignedlower-level terminal names in an instance. If Verilog-HDL is convertedinto VHDL, or if it is desired to show explicitly that the terminals areunassigned ones, however, it is more convenient to recite all the lowerlevel terminal names, and thus modification rule 53 a (Verilog instanceport: adjust to module port;)—all the terminal names (port names) are tobe recited in each instance—is defined/registered in hierarchyinformation template 53 as the control information.

[0120] Referring now to HDL description 2A of FIG. 5, although fourterminal names “s”, “t”, “u”, and “v” are shown in the lower level, theterminal name “v” is not recited in the instance in the upper level, asa terminal having the terminal name “v” is an unassigned one. Once thisHDL description 2A is input to automated HDL modifying apparatus 1, thedescription “ins(.s(a),.t(b),.u(c))”, in which the unassigned terminalname “v” is omitted (hereinafter this kind of description will be called“omission description”), is automatically modified into“ins(.s(a),.t(b),.u(c),.v( ))”, in which all the terminal names arerecited, in modified HDL description 2B. And further, at the end of eachmodified line, comment attaching means 20 attaches a modificationcomment “//CORRECTED”. Hereby, even unassigned terminals, if any, areexplicitly shown, and conversion of the description from Verilog-HDLinto VHDL is attainable.

[0121] Referring now to FIG. 6, in HDL description 2A in Verilog-HDL,output u is described to take two bits [0:1] in the lower level, whilein the upper level, output c, which corresponds to output u, isdescribed to be one bit, with the omission of description of theremaining unused one bit of output u in the instance.

[0122] At that time, if modification rule 53 b (bundle port: adjust tolower module)—in case of disagreement in bit width between two or morehierarchical levels, the bit width in the instance in an upper levelshould be matched to that of the module in a lower level—isdefined/registered in hierarchy information template 53 as controlinformation, HDL description 2A of FIG. 6 is automatically modified intomodified HDL description 2B, in which the bit width description in theupper level in the instance is matched with that in the lower level, andthen at the end of each modified line, a modification comment“//CORRECTED” is attached. Hereby, it is made clear that in the upperlevel, one of the two bits of output u is unused.

[0123] Additionally, in modified HDL description 2B of FIG. 6, 2-bitsignal d is newly defined (wire[0:1] d;), and one of the two bits ofsignal d is assigned to signal c (assign c=d[0];), and also, signal dand output u are associated with one another (“ins(.s(a),.t(b),.u(d))”).

[0124] In a hierarchical HDL description 2A described in VHDL, if acomponent port description in an upper level is consistent with anentity port description in a lower level, it is sometimes impossible tocollectively process both the upper and lower levels. For example, inHDL description 2A of FIG. 7, entity port name V is written in the lowerlevel, while the port name V is omitted in the upper level since a porthaving port name V is not assigned.

[0125] At that time, if modification rule 53 c (component port:complement to entity)—a component description in an upper level shouldbe matched to an entity port description in a lower level—isdefined/registered in hierarchy information template 53 as controlinformation, omission descriptions “port(S,T:in std_logic;U:outstd_logic” and “port map(S=>A,T=>B,U=>C)” in HDL description 2A of FIG.7 are automatically modified into “port(S,T:in std_logic;U,V:outstd_logic” and “port map(S=>A, T=>B, U=>C, V=>OPEN)”, respectively, inwhich the component description in the upper level is matched to theentity port description in the lower level. And further, the end of eachmodified line, comment attaching means 20 attaches a modificationcomment “//CORRECTED”. Hereby, it is made clear that unassigned port Vexists in the upper level.

[0126] Referring now to HDL description 2A of FIG. 8, portposition-adapted descriptions and port name-adapted descriptions areboth grammatically correct, but with the necessity of the uniformity ofthe descriptions, modification rule 53 d (port connection:name;)—portnames (terminal names) in instances should be written in a uniformfashion, in either of a name-adapted or a position-adapted fashion—isdefined/registered in hierarchy information template 53 as controlinformation.

[0127] For example, as shown in FIG. 8, if HDL description 2A isdescribed in a port position-adapted fashion, and also if modificationrule 53 d instructs the description to be modified into a portname-adapted fashion, “test1 test1_ins (p, q);” in HDL description 2A isautomatically modified into “test1 test1_ins(.a(p),.b(q));” in modifiedHDL description 2B, and at the end of the modified line, commentattaching means 20 attaches a modification comment “//CORRECTED”.Hereby, port names (terminal names) are described in instances in auniform fashion, either of a name-adapted fashion or a position-adaptedfashion.

[0128] As described above, by appropriately defining object items andmodification rules in hierarchy information template 53, it is possibleto automatically modify the terminal descriptions which are inconsistentbetween a plurality of hierarchical levels of the HDL description 2A,into the descriptions which are consistent between all of the pluralhierarchical levels of the HDL description. Accordingly, it is possible,in an early stage, to detect and automatically modify such inappropriatedescriptions, which so far have been detected not by the front-end(language processor) but by the back-end (logic synthesis tool orverification tool), thereby surely preventing the occurrence ofreworking in the designing process.

[0129] [2-5] Modification Operation with Connection InformationTemplate:

[0130] In HDLs, since a signal assignment description is the basics ofoperational specification in the RTL (Register Transfer Level)description, there is a low possibility that the left side and the rightside of the description are confused. However, in structuredescriptions, since a huge amount of descriptions, though simple ones,are sometimes made, the possibility cannot be eliminated completely.Generally speaking, in HDLs, there are grammatical rules fordescriptions of ports (terminals) and signal assignment. In VHDL, inparticular, the following directions are defined for five types ofports, “in”, “out”, “inout”, “buffer”, and “linkage”. In other words, itis possible to represent on which side of the left one and the right oneof a signal assignment statement the above five types of ports are to bewritten, in the form of the following rules. in right side only out leftside only inout either of the two sides buffer either of the two sideslinkage either of the two sides

[0131] Likewise, in Verilog-HDL, the following directions are definedfor three types of ports, “input”, “output”, and “inout”. input rightside only output left side only inout either of the two sides

[0132] In automated HDL modifying apparatus 1 of the present embodiment,the above directions are applied as modification rules contained inconnection information template 54, and thereby, object item detectingmeans 17 detects a portion which yields an incorrect relationshipbetween the left side and the right side of a signal assignmentdescription, as an object item to be modified, and object item modifyingmeans 18 then modifies the thus detected incorrect relationship into acorrect one according to the above modification rules (directions).

[0133] For example, assuming the following signal assignment descriptionis included in HDL description 2A described in VHDL, it isinappropriate, yet not ungrammatical, that signal b of an outputterminal is input to input terminal a.

[0134] module test(a,b);

[0135] input a;

[0136] output b;

[0137] assign a=b;

[0138] endmodule

[0139] Here, the following modification rules are defined in connectioninformation template 54: input:right # input terminal must be on theright side output:left # output terminal must be on the left sideinout:both # inout terminal can be on either side

[0140] Hereby, the validity of the both sides of each signal assignmentdescription in HDL description 2A is checked. If any reverse descriptionis found, it is automatically modified, thereby generating/outputtingmodified HDL description 2B. At this time, also, at the end of themodified line, comment attaching means 20 attaches a modificationcomment “//CORRECTED”.

[0141] Consequently, the resulting modified HDL description 2B is asfollows:

[0142] module test(a,b);

[0143] input a;

[0144] output b;

[0145] assign b=a; //CORRECTED

[0146] endmodule

[0147] As described above, by appropriately defining object items andmodification rules in connection information template 54, it is possibleto automatically modify the portion in which the relationship betweenthe left side and the right side of a signal assignment description isincorrect, into a correct relationship. And also, by using differentmodification rules for different HDLs, it is possible to automaticallycarry out an appropriate modification according to the languagespecification of each HDL.

[0148] [2-6] Modification Operation with Synthesis-incapable DescriptionTemplate:

[0149] In an HDL description that is to be subjected to logic synthesis,there often remains a waveform observation-dedicated simulationdescription, which has been used in logic verification and is incapableof being logically synthesized, without being annotated.

[0150] Accordingly, in automated HDL modifying apparatus 1, modificationrule 55 a (see FIG. 9) of synthesis-incapable description template 55recites all the waveform observation-dedicated simulation descriptionswhich are incapable of being logically synthesized, and also designateswhether to delete the descriptions or to added/written-in directives forinstructing a logic synthesis tool to ignore the descriptions. At thattime, such directives are written so as to sandwich the correspondingdescription, and the logic synthesis tool ignores the sandwicheddescription, coping with the description as not being the subject oflogic synthesis. In this instance, it is a designer who decides whetherto delete or to ignore the description.

[0151] For example, in FIG. 9, modification rule 55 a ofsynthesis-incapable description template 55 recites initial statementand “$monitor( )” as logic-synthesis-incapable waveformobservation-dedicated simulation descriptions, and designates that thesedescriptions are to be sandwiched with synthesis on/off directives.

[0152] In HDL description 2A of FIG. 9, “initial o=1′b0;” and “$monitor(o);” are logic-synthesis-incapable waveform observation-dedicatedsimulation descriptions, which are detected by object item detectingmeans 17. Object item modifying means 18 automatically adds/writes-insynthesis off/on directives before and after the description (seemodified HDL description 2B of FIG. 9), and at the end of eachadded/written-in portion (modified portion), comment attaching means 20attaches a modification comment “//CORRECTED”.

[0153] Hereby, even if logic-synthesis-incapable waveformobservation-dedicated simulation descriptions “initial o=1′b0;” and“$monitor (o);”, which has been used in logic verification, remains inHDL description 2A without being annotated, there would be caused noproblems (errors) with a logic synthesis tool. Accordingly, it is nolonger required for designers to delete such synthesis-incapabledescriptions by manual operation, thereby significantly reducing burdensof the designers.

[0154] [3] Effects of one Embodiment:

[0155] In this manner, with automated HDL modifying apparatus 1 of oneembodiment of the present invention, it is possible to detectinappropriate descriptions in HDL description 2A, and it is alsopossible to generate modified HDL description 2B in which suchinappropriate descriptions have been modified into appropriatedescriptions, thereby guaranteeing high-quality HDL description 2B.

[0156] In the present embodiment, in particular, since serious semanticgrammar errors are automatically modified and the modified portions areclearly shown, it is possible to significantly reduce burdens ondesigners, and also possible to obtain high-quality modified HDLdescription 2B. Further, partly since a portion (corresponding toto-be-modified object item) which is not a grammar error but should beconsidered in view of circuit designing is automatically modified intoan appropriate description, and partly since the modified portion isclearly shown, it is possible to significantly reduce burdens ondesigners, and also possible to obtain high-quality modified HDLdescription 2B.

[0157] Still further, by appropriately defining object items andmodification rules in templates 51 through 55, it is possible to detectand automatically modify, in an early stage, a portion (an appropriatedescription) which should be considered in view of circuit designing andcareless mistakes made by designers, thereby surely preventing theoccurrence of reworking in the designing process.

[0158] Such inappropriate descriptions often express circuit functionsor structures that are apart from a designer's intention. The errorswould be discovered later in a subsequent logic verification process orin a circuit packaging process, and the modification operation would beaccordingly necessitate. With automated HDL modifying apparatus 1 of thepresent embodiment, however, such inappropriate descriptions aremodified earlier, at the time of generation of the HDL description,thereby eliminating future time-consuming modification operations.

[0159] Additionally, since modification comments (notes) are attached tomodified portions, clearly indicating the modified portions, thus makingit possible for a designer to visually recognize where and in what waythe modifications have been performed. Accordingly, it is also possiblefor the designer to check, with ease and certainty, whether or not theresults of the automatic modifications comply with their intentions, andthus burdens on the designer are significantly reduced.

[0160] Moreover, the modification comments attached to modified HDLdescription 2B inform the designers about in what situations they areapt to make modification-required descriptions, thereby exertingeducational effects on the designers.

[0161] [4] Others:

[0162] Further, the present invention should by no means be limited tothe above-illustrated embodiment, but various changes or modificationsmay be suggested without departing from the gist of the invention.

[0163] For example, although in the above embodiment, the explanationwas given in case where the HDL is VHDL or Verilog-HDL, the presentinvention would be applicable also to other languages. In this case,similar effects and profits to those in the above expressions are alsoguaranteed, and the present invention would significantly contribute tothe promoted efficiency and reduced efforts in the fields of circuitdesigning and software development.

What is claimed is:
 1. An apparatus for automatically modifying circuitdesign information (hereinafter called the HDL description) described ina hardware description language (HDL), said apparatus comprising: (a)HDL lexical analysis means for performing a lexical analysis of the HDLdescription which is to be modified; (b) HDL syntax analysis means forperforming a syntax analysis of the HDL description based on the resultof the lexical analysis by said HDL lexical analysis means, to convertthe HDL description into a parse tree format description; (c) semanticgrammar error detection means for performing semantic analysis of theHDL description based on the result of the syntax analysis by said HDLsyntax analysis means, detecting a portion of the HDL description, inwhich portion variables on right and left sides of an assignmentstatement are inconsistent in type, and regarding the detected portionas a semantic-grammar-error portion; (d) a type conversion template fordefining a type conversion function, which converts the type of thevariable on the right side of the assignment statement into that of thevariable on the left side of the assignment statement, as a typeconversion rule; (e) semantic grammar error modifying means formodifying said semantic-grammar-error portion into a correct descriptionby applying said type conversion function, which has been defined bysaid type conversion template, to the right side of the assignmentstatement which side has been regarded as said semantic-grammar-errorportion by said semantic grammar error detecting means; (f) HDL reversesyntax analysis means for performing a reverse syntax analysis of theHDL description, which has been modified by said semantic grammar errormodifying means, to convert the HDL description from said parse treeformat description into an ordinary format description; and (g) commentattaching means for attaching a comment about the modification to themodified portion, which is the portion as the result of the modificationby said semantic grammar error modifying means.
 2. An apparatusaccording to claim 1, further comprising: (h) a control informationtemplate for defining a to-be-modified item (hereinafter called “objectitem”), which is not a grammar error but should be considered in view ofcircuit designing, and a modification rule to modify said object item;(i) object item detecting means for detecting a portion corresponding tosaid object item in the HDL description, based on the result of thesyntax analysis by said HDL syntax analysis means; and (j) object itemmodifying means for modifying the last-named corresponding portion,which has been detected by said object item detecting means, inaccordance with said modification rule defined by said controlinformation template; said HDL reverse syntax analysis means beingoperable to perform a reverse syntax analysis of the modified HDLdescription, which is the description as the result of the modificationby said semantic grammar error modifying means and said object itemmodifying means; said comment attaching means being operable to attach acomment about the modification to the modified corresponding portion,which is the portion as the result of the modification by said semanticgrammar error modifying means and said object item modifying means. 3.An apparatus for automatically modifying circuit design information(hereinafter called the HDL description) described in a hardwaredescription language (HDL), said apparatus comprising: (a) HDL lexicalanalysis means for performing a lexical analysis of the HDL descriptionwhich is to be modified; (b) HDL syntax analysis means for performing asyntax analysis of the HDL description based on the result of thelexical analysis by said HDL lexical analysis means, to convert the HDLdescription into a parse tree format description; (c) a controlinformation template for defining a to-be-modified item (hereinaftercalled “object item”), which is not a grammar error but should beconsidered in view of circuit designing, and a modification rule tomodify said object item; (d) object item detecting means for detecting aportion corresponding to said object item in the HDL description, basedon the result of the syntax analysis by said HDL syntax analysis means;(e) object item modifying means for modifying the last-namedcorresponding portion, which has been detected by said object itemdetecting means, in accordance with said modification rule defined bysaid control information template; (f) HDL reverse syntax analysis meansfor performing reverse syntax analysis of the modified HDL description,which is the description as the result of the modification by saidobject item modifying means, to convert the HDL description from saidparse tree format description into an ordinary description; and (g)comment attaching means for attaching a comment about the modificationto the modified corresponding portion, which is the portion as theresult of the modification by said object item modifying means.
 4. Anapparatus according to claim 2, wherein said control informationtemplate defines: said object item in such a manner that, on theassumption that the HDL being currently modified is converted intoanother HDL, said object item detecting means detects a portion of thecurrent HDL description, which portion does not comply with languagerules of the second-named HDL, as a portion corresponding to said objectitem; and said modification rule in such a manner that said object itemmodifying means modifies the last-named corresponding portion, which hasbeen detected by said object item detecting means, into a descriptionthat complies with the language rules of said second-named HDL.
 5. Anapparatus according to claim 3, wherein said control informationtemplate defines: said object item in such a manner that, on theassumption that the HDL being currently modified is converted intoanother HDL, said object item detecting means detects a portion of thecurrent HDL description, which portion does not comply with languagerules of the second-named HDL, as a portion corresponding to said objectitem; and said modification rule in such a manner that said object itemmodifying means modifies the last-named corresponding portion, which hasbeen detected by said object item detecting means, into a descriptionthat complies with the language rules of said second-named HDL.
 6. Anapparatus according to claim 4, wherein if the current HDL iscase-sensitive, in consideration of a possibility that the current HDLmight be converted into another HDL that is case-insensitive, saidcontrol information template defines: said object item in such a mannerthat said object item detecting means detects one of a pair of characterstrings which are composed of common characters arranged in the sameorder and described case-sensitively, as a portion corresponding to saidobject item; and said modification rule in such a manner that saidobject item modifying means modifies the last-named correspondingportion, which has been detected by said object item detecting means, bygenerating a new character string that is not contained in the HDLdescription, and then replacing said one of the two character strings,which has been detected by said object item detecting means, with saidnew character string.
 7. An apparatus according to claim 5, wherein ifthe current HDL is case-sensitive, in consideration of a possibilitythat the current HDL might be converted into another HDL that iscase-insensitive, said control information template defines: said objectitem in such a manner that said object item detecting means detects oneof a pair of character strings which are composed of common charactersarranged in the same order and described case-sensitively, as a portioncorresponding to said object item; and said modification rule in such amanner that said object item modifying means modifies the last-namedcorresponding portion, which has been detected by said object itemdetecting means, by generating a new character string that is notcontained in the HDL description, and then replacing said one of the twocharacter strings, which has been detected by said object item detectingmeans, with said new character string.
 8. An apparatus according toclaim 4, wherein if the current HDL is case-insensitive, inconsideration of a possibility that the current HDL might be convertedinto another HDL that is case-sensitive, said control informationtemplate defines: said object item in such a manner that said objectitem detecting means detects every upper case character or every lowercase character in a character string, as a portion corresponding to saidobject item; and said modification rule in such a manner that saidobject item modifying means modifies the last-named correspondingportion, which has been detected by said object item detecting means, byconverting every upper case character into a lower case character, orevery lower case character into an upper case character.
 9. An apparatusaccording to claim 5, wherein if the current HDL is case-insensitive, inconsideration of a possibility that the current HDL might be convertedinto another HDL that is case-sensitive, said control informationtemplate defines: said object item in such a manner that said objectitem detecting means detects every upper case character or every lowercase character in a character string, as a portion corresponding to saidobject item; and said modification rule in such a manner that saidobject item modifying means modifies the last-named correspondingportion, which has been detected by said object item detecting means, byconverting every upper case character into a lower case character, orevery lower case character into an upper case character.
 10. Anapparatus according to claim 2, wherein said control informationtemplate defines: said object item in such a manner that said objectitem detecting means detects a character string which includes apredetermined prohibited character, as a portion corresponding to saidobject item; and said modification rule in such a manner that saidobject item modifying means modifies the last-named correspondingportion, which has been detected by said object item detecting means, bygenerating a new character string which neither is contained in the HDLdescription nor includes said predetermined prohibited character, andthen replacing the prohibited-character-included character string, whichhas been detected by said object item detecting means, with said newcharacter string.
 11. An apparatus according to claim 3, wherein saidcontrol information template defines: said object item in such a mannerthat said object item detecting means detects a character string whichincludes a predetermined prohibited character, as a portioncorresponding to said object item; and said modification rule in such amanner that said object item modifying means modifies the last-namedcorresponding portion, which has been detected by said object itemdetecting means, by generating a new character string which neither iscontained in the HDL description nor includes said predeterminedprohibited character, and then replacing theprohibited-character-included character string, which has been detectedby said object item detecting means, with said new character string. 12.An apparatus according to claim 2, wherein said control informationtemplate defines: said object item in such a manner that said objectitem detecting means detects a portion of the HDL description, whichportion is inconsistent in terminal description between a plurality ofhierarchical levels of the HDL description, as a portion correspondingto said object item; and said modification rule in such a manner thatsaid object item modifying means modifies the inconsistent terminaldescription in the last-named corresponding portion, which has beendetected by said object item detecting means, into a correct descriptionwhich is consistent between all of the plural hierarchical levels of theHDL description.
 13. An apparatus according to claim 3, wherein saidcontrol information template defines: said object item in such a mannerthat said object item detecting means detects a portion of the HDLdescription, which portion is inconsistent in terminal descriptionbetween a plurality of hierarchical levels of the HDL description, as aportion corresponding to said object item; and said modification rule insuch a manner that said object item modifying means modifies theinconsistent terminal description in the last-named correspondingportion, which has been detected by said object item detecting means,into a correct description which is consistent between all of the pluralhierarchical levels of the HDL description.
 14. An apparatus accordingto claim 2, wherein said control information template defines: saidobject item in such a manner that said object item detecting meansdetects a portion of the HDL description, which portion yields anincorrect relationship between the left and the right sides of a signalassignment description, as a portion corresponding to said object item;and said modification rule in such a manner that said object itemmodifying means modifies the last-named corresponding portion, which hasbeen detected by said object item detecting means, into a correctdescription which yields a correct relationship between the left and theright sides of said signal assignment description.
 15. An apparatusaccording to claim 3, wherein said control information template defines:said object item in such a manner that said object item detecting meansdetects a portion of the HDL description, which portion yields anincorrect relationship between the left and the right sides of a signalassignment description, as a portion corresponding to said object item;and said modification rule in such a manner that said object itemmodifying means modifies the last-named corresponding portion, which hasbeen detected by said object item detecting means, into a correctdescription which yields a correct relationship between the left and theright sides of said signal assignment description.
 16. An apparatusaccording to claim 2, wherein said control information template defines:said object item in such a manner that said object item detecting meansdetects a portion of the HDL description, which portion is unable to besynthesized by a logic synthesis tool, as a portion corresponding tosaid object item; and said modification rule in such a manner that saidobject item modifying means deletes the last-named correspondingportion, which has been detected by said object item detecting means.17. An apparatus according to claim 3, wherein said control informationtemplate defines: said object item in such a manner that said objectitem detecting means detects a portion of the HDL description, whichportion is unable to be synthesized by a logic synthesis tool, as aportion corresponding to said object item; and said modification rule insuch a manner that said object item modifying means deletes thelast-named corresponding portion, which has been detected by said objectitem detecting means.
 18. An apparatus according to claim 2, whereinsaid control information template defines: said object item in such amanner that said object item detecting means detects a portion of theHDL description, which portion is unable to be synthesized by a logicsynthesis tool, as a portion corresponding to said object item; and saidmodification rule in such a manner that said object item modifying meansadds to the last-named corresponding portion, which has been detected bysaid object item detecting means, a directive for instructing said logicsynthesis tool to ignore said last-named corresponding portion.
 19. Anapparatus according to claim 3, wherein said control informationtemplate defines: said object item in such a manner that said objectitem detecting means detects a portion of the HDL description, whichportion is unable to be synthesized by a logic synthesis tool, as aportion corresponding to said object item; and said modification rule insuch a manner that said object item modifying means adds to thelast-named corresponding portion, which has been detected by said objectitem detecting means, a directive for instructing said logic synthesistool to ignore said last-named corresponding portion.
 20. Acomputer-readable recording medium in which a program for automaticallymodifying circuit design information (hereinafter called the HDLdescription) described in a hardware description language (HDL) isrecorded, wherein said program instructs a computer to function as thefollowing: (a) HDL lexical analysis means for performing a lexicalanalysis of the HDL description which is to be modified; (b) HDL syntaxanalysis means for performing a syntax analysis of the HDL descriptionbased on the result of the lexical analysis by said HDL lexical analysismeans, to convert the HDL description into a parse tree formatdescription; (c) semantic grammar error detection means for performing asemantic analysis of the HDL description based on the result of thesyntax analysis by said HDL syntax analysis means, detecting a portionof the HDL description, in which portion variables on right and leftsides of an assignment statement are inconsistent in type, and regardingthe detected portion as a semantic-grammar-error portion; (d) semanticgrammar error modifying means for modifying said semantic-grammar-errorportion into a correct description by applying a type conversionfunction, which converts the type of the variable on the right side ofthe assignment statement into that of the variable on the left side ofthe assignment statement, to the right side of the assignment statementwhich side has been regarded as said semantic-grammar-error portion bysaid semantic grammar error detecting means; (e) HDL reverse syntaxanalysis means for performing a reverse syntax analysis of the HDLdescription, which has been modified by said semantic grammar errormodifying means, to convert the HDL description from said parse treeformat description into an ordinary format description; and (f) commentattaching means for attaching a comment about the modification to themodified portion, which is the portion as the result of the modificationby said semantic grammar error modifying means.
 21. A computer-readablerecording medium according to claim 20, wherein said program furtherinstructs the computer to function as the following: (g) object itemdetecting means for detecting a portion corresponding to ato-be-modified item (hereinafter called “object item”) in the HDLdescription, which item is not a grammar error but should be consideredin view of circuit designing, based on the result of the syntax analysisby said HDL syntax analysis means; and (h) object item modifying meansfor modifying the last-named corresponding portion, which has beendetected by said object item detecting means, in accordance with amodification rule which has been defined previously for said objectitem; said HDL reverse syntax analysis means being operable to perform areverse syntax analysis of the modified HDL description, which is thedescription as the result of the modification by said semantic grammarerror modifying means and said object item modifying means; said commentattaching means being operable to attach a comment about themodification to the modified corresponding portion, which is the portionas the result of the modification by said semantic grammar errormodifying means and said object item modifying means.
 22. Acomputer-readable recording medium in which a program for automaticallymodifying circuit design information (hereinafter called the HDLdescription) described in a hardware description language (HDL) isrecorded, wherein said program instructs a computer to function as thefollowing: (a) HDL lexical analysis means for performing a lexicalanalysis of the HDL description which is to be modified; (b) HDL syntaxanalysis means for performing a syntax analysis of the HDL descriptionbased on the result of the lexical analysis by said HDL lexical analysismeans, to convert the HDL description into a parse tree formatdescription; (c) object item detecting means for detecting a portioncorresponding to a to-be-modified item (hereinafter called “objectitem”) in the HDL description, which item is not a grammar error butshould be considered in view of circuit designing, based on the resultof the syntax analysis by said HDL syntax analysis means; (d) objectitem modifying means for modifying the last-named corresponding portion,which has been detected by said object item detecting means, inaccordance with a modification rule which has been defined previouslyfor said object item; (e) HDL reverse syntax analysis means forperforming a syntax analysis of the modified HDL description, which isthe description as the result of the modification by said object itemmodifying means, to convert the HDL description from said parse treeformat description into an ordinary format description; and (f) commentattaching means for attaching a comment about the modification to themodified corresponding portion, which is the portion as the result ofthe modification by said object item modifying means.